Journal of Multidisciplinary Applied Natural Science
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4.8
Calculated on 05 May, 2025
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https://doi.org/10.47352/jmans.2774-3047.331
Shylaja Veerabhadraiah
N Kannan
T Y Satheesha
The Arithmetic Logic Unit (ALU) is a fundamental component for executing arithmetic and logical operations in digital systems. However, existing ALU designs often overlook variations in photoresist thickness during fabrication, leading to increased gate leakage and reduced reliability. This paper proposes a power-efficient 4-bit ALU design that is aware of photoresist thickness fluctuations, leveraging Pareto Distribution Reverse Body Biasing (PD-RBB) and Singer Spider Map Wasp Optimization (2SMWO). Fluctuation detection and mitigation are achieved through a Bernstein Polynomial Sigmoid Fuzzy Inference System (BPS-FIS), while leakage current and transistor failures are addressed using PD-RBB and Wishart Distribution-based Triple Modular Redundancy (Wd-TMR), respectively. To enhance reversibility and reduce power loss, the Golay Ternary Reversible Gate (GTRG) is integrated. Division complexity is managed via Sigmoid-based Correction Non-Restoring Division (SbC-NRD), and a Carry Look-Ahead Adder (CLAA) supports parallel processing. Experimental results demonstrate a 92% reduction in leakage current, confirming the effectiveness of the proposed approach in improving power efficiency and reliability.
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